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Isolated Preset Architecture for a 32nm SOI embedded DRAM macro.

J. Barth, D. Plass, A. Vehabovic, R. Joshi, R. Kanj, S. Burns, and T. Weaver. VLSIC, page 110-111. IEEE, (2012)

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Calum Burns

Barbara Burns

Nicola Burns

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John Burns

Other publications of authors with the same name

17.4 A 14nm 1.1Mb embedded DRAM macro with 1ns access.G. Fredeman, D. Plass, A. Mathews, K. Reyer, T. Knips, T. Miller, E. Gerhard, D. Kannambadi, C. Paone, D. Lee and 4 other author(s). ISSCC, page 1-3. IEEE, (2015)Online Data Visualization of Multidimensional Databases Using the Hilbert Space-Filling Curve.J. Castro, and S. Burns. VIEW, volume 4370 of Lecture Notes in Computer Science, page 92-109. Springer, (2006)12.4 1.4Gsearch/s 2Mb/mm2 TCAM using two-phase-precharge ML sensing and power-grid preconditioning to reduce Ldi/dt power-supply noise by 50%.I. Arsovski, M. Fragano, R. Houle, A. Patil, V. Butler, R. Kim, R. Rodriguez, T. Maffitt, J. Oler, J. Goss and 3 other author(s). ISSCC, page 212-213. IEEE, (2017)Isolated Preset Architecture for a 32nm SOI embedded DRAM macro.J. Barth, D. Plass, A. Vehabovic, R. Joshi, R. Kanj, S. Burns, and T. Weaver. VLSIC, page 110-111. IEEE, (2012)The ISPD-2012 discrete cell sizing contest and benchmark suite.M. Ozdal, C. Amin, A. Ayupov, S. Burns, G. Wilke, and C. Zhuo. ISPD, page 161-164. ACM, (2012)Comparative Analysis of Conventional and Statistical Design Techniques.S. Burns, M. Ketkar, N. Menezes, K. Bowman, J. Tschanz, and V. De. DAC, page 238-243. IEEE, (2007)A Charge Flow Formulation for Guiding Analog/Mixed-Signal Placement.T. Dhar, R. S, J. Poojary, S. Yaldiz, S. Burns, R. Harjani, and S. Sapatnekar. DATE, page 148-153. IEEE, (2022)Reusing GEMM Hardware for Efficient Execution of Depthwise Separable Convolution on ASIC-Based DNN Accelerators.S. Manasi, S. Banerjee, A. Davare, A. Sorokin, S. Burns, D. Kirkpatrick, and S. Sapatnekar. ASP-DAC, page 475-482. ACM, (2023)Energy Efficient Architecture for Graph Analytics Accelerators.M. Ozdal, S. Yesil, T. Kim, A. Ayupov, J. Greth, S. Burns, and Ö. Özturk. ISCA, page 166-177. IEEE Computer Society, (2016)Learning from Experience: Applying ML to Analog Circuit Design.K. Kunal, T. Dhar, Y. Li, M. Madhusudan, J. Poojary, A. Sharma, W. Xu, S. Burns, R. Harjani, J. Hu and 2 other author(s). ISPD, page 55. ACM, (2020)

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Disambiguation of "Burns, Steven"

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Isolated Preset Architecture for a 32nm SOI embedded DRAM macro.

Please choose a person to relate this publication to

Calum Burns

Barbara Burns

Nicola Burns

Glen Burns

John Burns

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Burns, Steven"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Isolated Preset Architecture for a 32nm SOI embedded DRAM macro.

Please choose a person to relate this publication to

Calum Burns

Barbara Burns

Nicola Burns

Glen Burns

John Burns

Other publications of authors with the same name

Disambiguation

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DOI
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APA
Chicago
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Isolated Preset Architecture for a 32nm SOI embedded DRAM macro.