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Disambiguation of "Lee, Jeong-Gun"

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Design of a Mutated Adder and Its Optimization Using ILP Formulation.

, , , and . IEICE Trans. Inf. Syst., 88-D (7): 1506-1508 (2005)

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Jeong-Hoon Lee

Yoo-Jeong Lee

Eun-Jeong Lee

Jeong-Keun Lee

Jeong-Hoon Lee

 

Other publications of authors with the same name

A high-resolution and glitch-free all-digital variable length ring oscillator design on an FPGA., , and . Comput. Electr. Eng., (2019)A Performance/Energy Analysis and Optimization of Multi-Core Architectures with Voltage Scaling Techniques., , , and . IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 93-A (6): 1215-1225 (2010)Design of a Mutated Adder and Its Optimization Using ILP Formulation., , , and . IEICE Trans. Inf. Syst., 88-D (7): 1506-1508 (2005)Asynchronous Circuit Designs on an FPGA for Targeting a Power/Energy Efficient SoC., and . IEICE Trans. Electron., 97-C (4): 253-263 (2014)Instruction level redundant number computations for fast data intensive processing in asynchronous processors., , and . J. Syst. Archit., 51 (3): 151-164 (2005)Low area and high speed SHA-1 implementation., , and . ISOCC, page 365-367. IEEE, (2011)A Design Method for Heterogeneous Adders., , , and . ICESS, volume 4523 of Lecture Notes in Computer Science, page 121-132. Springer, (2007)Performance optimization of synchronous control units for datapaths with variable delay arithmetic units., , , , , and . ASP-DAC, page 816-819. ACM, (2003)Measurements of metastability in MUTEX on an FPGA., , and . IEICE Electron. Express, 15 (1): 20171165 (2018)Implications of Rent's Rule for NoC Design and Its Fault-Tolerance., , , and . NOCS, page 283-294. IEEE Computer Society, (2007)