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Low-power digital systems based on adiabatic-switching principles.

, , , , and . IEEE Trans. Very Large Scale Integr. Syst., 2 (4): 398-407 (1994)

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A 40-44 Gb/s 3 × Oversampling CMOS CDR/1: 16 DEMUX., , , , , , , , , and . IEEE J. Solid State Circuits, 42 (12): 2726-2735 (2007)A 3 Watt 39.8-44.6 Gb/s Dual-Mode SFI5.2 SerDes Chip Set in 65 nm CMOS., , , , , , , , , and 13 other author(s). IEEE J. Solid State Circuits, 45 (10): 2016-2029 (2010)Clock-Powered CMOS: A Hybrid Adiabatic Logic Style for Energy-Efficient Computing., and . ARVLSI, page 137-153. IEEE Computer Society, (1999)A 40-to-44Gb/s 3�? Oversampling CMOS CDR/1: 16 DEMUX., , , , , , , , , and . ISSCC, page 224-598. IEEE, (2007)A low-power microprocessor based on resonant energy., , , and . IEEE J. Solid State Circuits, 32 (11): 1693-1701 (1997)Energy recovery for low-power CMOS., and . ARVLSI, page 415-429. IEEE Computer Society, (1995)Retractile clock-powered logic., and . ISLPED, page 18-23. ACM, (1999)A leakage current replica keeper for dynamic circuits., , and . ISSCC, page 1755-1764. IEEE, (2006)A Reversible Poly-Phase Distributed VCO., and . ISSCC, page 2452-2461. IEEE, (2006)AC-1: a clock-powered microprocessor., , , , , , , and . ISLPED, page 328-333. ACM, (1997)