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Parallel H.264 Decoding on an Embedded Multicore Processor.

, , , , , , and . HiPEAC, volume 5409 of Lecture Notes in Computer Science, page 404-418. Springer, (2009)

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When reconfigurable architecture meets network-on-chip., , and . SBCCI, page 216-221. ACM, (2004)MoCHA: a Bi-Predictive Motion Compensation Hardware for H.264/AVC Decoder Targeting HDTV., , , and . ISCAS, page 1617-1620. IEEE, (2007)Analysis of video filtering on the cell processor., , , , and . ISCAS, page 488-491. IEEE, (2008)X4CP32: A New Parallel/Reconfigurable General-Purpose Processor., , and . SBAC-PAD, page 260-268. IEEE Computer Society, (2003)Parallel Scalability of Video Decoders., , , , and . J. Signal Process. Syst., 57 (2): 173-194 (2009)An Instruction to Accelerate Software Caches., and . ARCS, volume 6566 of Lecture Notes in Computer Science, page 158-170. Springer, (2011)Evaluación del rendimiento paralelo en el nivel macro bloque del decodificador H.264 en una arquitectura multiprocesador cc-NUMA., , , , and . Rev. Avances en Sistemas Informática, 6 (1): 219-228 (2009)A Highly Scalable Parallel Implementation of H.264., , , , , , , and . Trans. High Perform. Embed. Archit. Compil., (2011)A reduced memory bandwidth and high throughput HDTV motion compensation decoder for H.264/AVC High 4: 2: 2 profile., , , , , and . J. Real Time Image Process., 8 (1): 127-140 (2013)An efficient software cache for H.264 motion compensation., and . SoC, page 147-150. IEEE, (2009)