Author of the publication

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Parasitic-aware Sizing and Detailed Routing for Binary-weighted Capacitors in Charge-scaling DAC.

M. Lin, V. Hsiao, and C. Lin. DAC, page 165:1-165:6. ACM, (2014)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Po-Lin Hsu

Lin-Po Li

Yin-Hung Lin

Jr-Hung Lin

Lin Lin

Other publications of authors with the same name

Analog Placement Based on Novel Symmetry-Island Formulation.M. Lin, and S. Lin. DAC, page 465-470. IEEE, (2007)Minimizing detection-to-boosting latency toward low-power error-resilient circuits.C. Hsu, M. Hashimoto, and M. Lin. Integr., (2017)Exploring Feasibilities of Symmetry Islands and Monotonic Current Paths in Slicing Trees for Analog Placement.P. Wu, M. Lin, T. Chen, C. Yeh, T. Ho, and B. Liu. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 33 (6): 879-892 (2014)Analog Placement Based on Symmetry-Island Formulation.M. Lin, Y. Chang, and S. Lin. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 28 (6): 791-804 (2009)Performance-driven analog placement considering monotonic current paths.P. Wu, M. Lin, Y. Chen, B. Chou, T. Chen, T. Ho, and B. Liu. ICCAD, page 613-619. ACM, (2012)Post-placement power optimization with multi-bit flip-flops.Y. Chang, C. Hsu, M. Lin, Y. Tsai, and S. Chen. ICCAD, page 218-223. IEEE, (2010)Reinforcement Learning or Simulated Annealing for Analog Placement? A Study based on Bounded-Sliceline Grids.M. Lin, C. Lee, and Y. Hsieh. ISPD, page 143-150. ACM, (2024)Automated synthesis of discrete-time sigma-delta modulators from system architecture to circuit netlist.S. Lee, C. Chen, J. Hong, R. Chang, and M. Lin. Microelectron. J., 42 (2): 347-357 (2011)On Optimizing Capacitor Array Design for Advanced Node SAR ADC.C. Chiang, C. Hu, K. Chang, M. Lin, S. Jou, H. Chen, C. Liu, and H. Chen. SMACD, page 1-4. IEEE, (2022)A Novel Machine-Learning based SoC Performance Monitoring Methodology under Wide-Range PVT Variations with Unknown Critical Paths.D. Wang, P. Lin, H. Yang, C. Hsu, S. Huang, and M. Lin. DAC, page 1370-1371. IEEE, (2021)

BibSonomy

Disambiguation of "Lin, Mark Po-Hung"

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Parasitic-aware Sizing and Detailed Routing for Binary-weighted Capacitors in Charge-scaling DAC.

Please choose a person to relate this publication to

Po-Lin Hsu

Lin-Po Li

Yin-Hung Lin

Jr-Hung Lin

Lin Lin

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Lin, Mark Po-Hung"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Parasitic-aware Sizing and Detailed Routing for Binary-weighted Capacitors in Charge-scaling DAC.

Please choose a person to relate this publication to

Po-Lin Hsu

Lin-Po Li

Yin-Hung Lin

Jr-Hung Lin

Lin Lin

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Parasitic-aware Sizing and Detailed Routing for Binary-weighted Capacitors in Charge-scaling DAC.