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Disambiguation of "U., Seng-Pan"

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Timing-mismatch analysis in high-speed analog front-end with nonuniformly holding output.

, , , and . ISCAS (1), page 129-132. IEEE, (2003)

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Peter Seng

Stefan Seng

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Helmut Seng

Gerhard Seng

 

Other publications of authors with the same name

A frequency up-conversion and two-step channel selection embedded CMOS D/A interface., , , , and . ISCAS (1), page 392-395. IEEE, (2005)A novel low-voltage finite-gain compensation technique for high-speed reset- and switched-opamp circuits., , and . ISCAS, IEEE, (2006)New impulse sampled IIR switched-capacitor interpolators., , and . ICECS, page 203-206. IEEE, (1996)An 11b 60MS/s 2.1mW two-step time-interleaved SAR-ADC with reused S&H., , , , , , , , and . ESSCIRC, page 218-221. IEEE, (2010)A 4.2-mW 77.1-dB SNDR 5-MHz BW DT 2-1 MASH Δ Σ Modulator With Multirate Opamp Sharing., , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 64-I (10): 2641-2654 (2017)A 10-bit 500-MS/s Partial-Interleaving Pipelined SAR ADC With Offset and Reference Mismatch Calibrations., , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (1): 354-363 (2017)A linear-phase halfband SC video interpolation filter with coefficient-sharing and spread-reduction., , and . ISCAS, page 177-180. IEEE, (2000)A 34fJ 10b 500 MS/s partial-interleaving pipelined SAR ADC., , , , and . VLSIC, page 90-91. IEEE, (2012)A 7-bit 300-MS/s subranging ADC with embedded threshold & gain-loss calibration., , , , , and . ESSCIRC, page 363-366. IEEE, (2011)Jitter-resistant Capacitor Based Sine-Shaped DAC for Continuous-Time Sigma-Delta modulators., , , , and . ISCAS, page 1348-1351. IEEE, (2014)