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Modeling IP Responses in Testcase Generation for Systems-on-Chip Verification.

, , , , , and . MTV, page 7-10. IEEE Computer Society, (2003)

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Large-Scale Sorting in Uniform Memory Hierarchies., and . J. Parallel Distributed Comput., 17 (1-2): 107-114 (1993)Enhancing Sequential LEC Using a Cumulative Verification Methodology., , , and . MTV, page 39-42. IEEE Computer Society, (2008)MDD with Added Null-Value and All-Value Edges Applied to Multi-Valued Domino Logic Gates., and . J. Multiple Valued Log. Soft Comput., 15 (4): 379-394 (2009)I/O Overhead and Parallel VLSI Architectures for Lattice Computations., , and . ICCI, volume 468 of Lecture Notes in Computer Science, page 497-506. Springer, (1990)I/O Overhead and Parallel VLSI Architectures for Lattice Computations., , and . IEEE Trans. Computers, 40 (7): 843-852 (1991)Modeling IP Responses in Testcase Generation for Systems-on-Chip Verification., , , , , and . MTV, page 7-10. IEEE Computer Society, (2003)Blocking for External Graph Searching., , and . Algorithmica, 16 (2): 181-214 (1996)Greed Sort: Optimal Deterministic Sorting on Parallel Disks., and . J. ACM, 42 (4): 919-933 (1995)Semantic Cardinality Estimation for Queries over Objects., , and . POS, page 164-173. Morgan Kaufmann, (1996)Deterministic Distribution Sort in Shared and Distributed Memory Multiprocessors., and . SPAA, page 120-129. ACM, (1993)