( en | de | ru )

 

Disambiguation of "Delgado-Frias, José G."

Author of the publication

copydeleteadd this publication to your clipboard
A VLSI-Processing and Communicating Pipelined Tree for Parallel Computing.

, and . Parallel and Distributed Computing and Systems, page 455-458. IASTED/ACTA Press, (1995)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

José Onelio Blanco Delgado

Armando José Oropeza Delgado

José Miguel Martins Delgado

Humberto Jorge José

Nadine José Gonzalez

 

Other publications of authors with the same name

On Throughput of Multipath Data Transmission over Multihop Ad Hoc Networks., and . Wireless and Optical Communications, IASTED/ACTA Press, (2006)A Two-Level Reconfigurable Architecture for Digital Signal Processing., and . VLSI, page 21-27. CSREA Press, (2003)A Pattern-Associative Router for Adaptive Algorithms in Hypercube Networks., , and . Parallel and Distributed Computing and Systems, page 238-242. IASTED/ACTA Press, (1995)An H-Tree Based Configuration Scheme for Reconfigurable DSP Hardware., and . ESA/VLSI, page 530-535. CSREA Press, (2004)A novel compaction scheme for routing tables in TCAM to enhance cache hit rate., and . Communications, Internet, and Information Technology, page 210-215. IASTED/ACTA Press, (2007)A wave-pipelined router architecture using ternary associative memory., , and . ACM Great Lakes Symposium on VLSI, page 67-70. ACM, (2000)A VLSI wrapped wave front arbiter for crossbar switches., and . ACM Great Lakes Symposium on VLSI, page 85-88. ACM, (2001)IP Routing table compaction and sampling schemes to enhance TCAM cache performance., and . J. Syst. Archit., 55 (1): 61-69 (2009)Preface., , , , , and . Integr., 40 (2): 61 (2007)A Medium-Grain Reconfigurable Architecture for DSP: VLSI Design, Benchmark Mapping, and Performance., and . IEEE Trans. Very Large Scale Integr. Syst., 16 (1): 14-23 (2008)