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POSTER: Design Space Exploration for Performance Optimization of Deep Neural Networks on Shared Memory Accelerators.

, , , , and . PACT, page 146-147. IEEE Computer Society, (2017)

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Workload-aware Automatic Parallelization for Multi-GPU DNN Training., , , , , and . CoRR, (2018)On the Nature of Cache Miss Behavior: Is It √2?, , , and . J. Instruction-Level Parallelism, (2008)ScaleCom: Scalable Sparsified Gradient Compression for Communication-Efficient Distributed Training., , , , , , , , , and 1 other author(s). CoRR, (2021)Efficient AI System Design With Cross-Layer Approximate Computing., , , , , , , , , and 30 other author(s). Proc. IEEE, 108 (12): 2232-2250 (2020)RECAP: A region-based cure for the common cold (cache)., , , , and . HPCA, page 83-94. IEEE Computer Society, (2013)Co-designing accelerators and SoC interfaces using gem5-Aladdin., , , , and . MICRO, page 48:1-48:12. IEEE Computer Society, (2016)Evaluating the performance of active cache management schemes., , , , and . ICCD, page 368-375. IEEE Computer Society, (1998)Big Chips., and . IEEE Micro, 31 (4): 3-5 (2011)Special Issue on Network and Parallel Computing., and . Int. J. Parallel Program., 45 (1): 1-3 (2017)Analyzing the Cost of a Cache Miss Using Pipeline Spectroscopy., , , , and . J. Instruction-Level Parallelism, (2008)