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Disambiguation of "Kurdahi, Fadi J."

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Techniques for area estimation of VLSI layouts.

, and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 8 (1): 81-92 (1989)

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Eckart Fadinger

Tolulope Rhoda Fadina

Fadi Gablawi

Fadi Hallak

Fadi Salti

 

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Partitioning by Regularity Extraction., and . DAC, page 235-238. IEEE Computer Society Press, (1992)Layout-driven RTL binding techniques for high-level synthesis using accurate estimators., and . ACM Trans. Design Autom. Electr. Syst., 2 (4): 312-343 (1997)A hierarchical pipelining architecture and FPGA implementation for lifting-based 2-D DWT., , and . J. Real-Time Image Processing, 2 (4): 281-291 (2007)Kernel scheduling techniques for efficient solution space exploration in reconfigurable computing., , , , , and . J. Syst. Archit., 47 (3-4): 277-292 (2001)Thermal sensor allocation for SoCs based on temperature gradients., , and . ISQED, page 29-34. IEEE, (2015)CAPPS: A Framework for Power-Performance Tradeoffs in Bus-Matrix-Based On-Chip Communication Architecture Synthesis., , , and . IEEE Trans. Very Large Scale Integr. Syst., 18 (2): 209-221 (2010)Automatic compilation to a coarse-grained reconfigurable system-opn-chip., , , , , and . ACM Trans. Embed. Comput. Syst., 2 (4): 560-589 (2003)System-level power-performance trade-offs in bus matrix communication architecture synthesis., , , and . CODES+ISSS, page 300-305. ACM, (2006)A unified lower bound estimation technique for high-level synthesis., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 16 (5): 458-472 (1997)Guest Editorial: Special Issue on Accelerated Computing., and . IEEE Trans. Multi Scale Comput. Syst., 4 (1): 1-2 (2018)