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Three Snakes in One Hole: The First Systematic Hardware Accelerator Design for SOSEMANUK with Optional Serpent and SNOW 2.0 Modes., and . IEEE Trans. Computers, 65 (2): 640-653 (2016)Complexity Analysis of Reversible Logic Synthesis., , and . CoRR, (2014)Efficient and Lightweight Quantized Compressive Sensing using μ-Law., , and . ISCAS, page 1-5. IEEE, (2018)System-level reliability exploration framework for heterogeneous MPSoC., , , and . ACM Great Lakes Symposium on VLSI, page 9-14. ACM, (2014)Towards Designing a Secure RISC-V System-on-Chip: ITUS., , , , , , and . J. Hardw. Syst. Secur., 4 (4): 329-342 (2020)Efficient Realization of Householder Transform Through Algorithm-Architecture Co-Design for Acceleration of QR Factorization., , , , , and . IEEE Trans. Parallel Distributed Syst., 29 (8): 1707-1720 (2018)Accelerating BLAS on Custom Architecture through Algorithm-Architecture Co-design., , , , , and . CoRR, (2016)Machine Learning based Blind Side-Channel Attacks on PQC-based KEMs - A Case Study of Kyber KEM., , , and . IACR Cryptol. ePrint Arch., (2024)SI-DFA: Sub-expression integrated Deterministic Finite Automata for Deep Packet Inspection., , and . HPSR, page 164-170. IEEE, (2013)Design and analysis of layered coarse-grained reconfigurable architecture., , and . ReConFig, page 1-6. IEEE, (2012)