( en | de | ru )

 

Disambiguation of "Narayanan, Vijaykrishnan"

Author of the publication

copydeleteadd this publication to your clipboard
Lifetime Reliability Aware Design Flow Techniques for Dual-Vdd Based Platform FPGAs.

, and . ISVLSI, page 61-66. IEEE Computer Society, (2009)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

P Narayanan

Hermine Narayanan

Vidya Narayanan

Narayanan Radhakrishnan

Narayanan Sundaram

 

Other publications of authors with the same name

Modeling steep slope devices: From circuits to architectures., , , , , , and . DATE, page 1-6. European Design and Automation Association, (2014)Influence of compiler optimizations on system power., , , and . DAC, page 304-307. ACM, (2000)Improving energy efficiency of multi-threaded applications using heterogeneous CMOS-TFET multicores., , , , , and . ISLPED, page 247-252. IEEE/ACM, (2011)GRAPHIC: Gather and Process Harmoniously in the Cache With High Parallelism and Flexibility., , , , , , , , , and 2 other author(s). IEEE Trans. Emerg. Top. Comput., 12 (1): 84-96 (January 2024)Robust Coreset Construction for Distributed Machine Learning., , , , , and . IEEE J. Sel. Areas Commun., 38 (10): 2400-2417 (2020)Power-efficient implementation of turbo decoder in SDR system., , , and . SoCC, page 119-122. IEEE, (2004)ChipPower: an architecture-level leakage simulator., , , , and . SoCC, page 395-398. IEEE, (2004)Hardware and Software Techniques for Controlling DRAM Power Modes., , , , and . IEEE Trans. Computers, 50 (11): 1154-1173 (2001)A low latency router supporting adaptivity for on-chip interconnects., , , , and . DAC, page 559-564. ACM, (2005)Design and analysis of an NoC architecture from performance, reliability and energy perspective., , , , and . ANCS, page 173-182. ACM, (2005)