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EVAX: Towards a Practical, Pro-active & Adaptive Architecture for High Performance & Security., , , , , and . MICRO, page 1218-1236. IEEE, (2022)POSTER: Fault-tolerant Execution on COTS Multi-core Processors with Hardware Transactional Memory Support., , , , and . PACT, page 421-422. ACM, (2016)Hurdle: Securing Jump Instructions Against Code Reuse Attacks., , , and . ASPLOS, page 653-666. ACM, (2020)ASPLOS 2020 was canceled because of COVID-19..PerSpectron: Detecting Invariant Footprints of Microarchitectural Attacks with Perceptron., , , , , and . MICRO, page 1124-1137. IEEE, (2020)Online Code Layout Optimizations via OCOLOS., , , , , and . IEEE Micro, 43 (4): 71-79 (July 2023)I-SPY: Context-Driven Conditional Instruction Prefetching with Coalescing., , , , , and . MICRO, page 146-159. IEEE, (2020)Huron: hybrid false sharing detection and repair., , , , and . PLDI, page 453-468. ACM, (2019)Invyswell: a hybrid transactional memory for haswell's restricted transactional memory., , , , and . PACT, page 187-200. ACM, (2014)The Case for Message Passing on Many-Core Chips., , , and . Multiprocessor System-on-Chip, Springer, (2011)TMI: thread memory isolation for false sharing repair., , , , and . MICRO, page 639-650. ACM, (2017)