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An evaluation of hardware-based and compiler-controlled optimizations of snooping cache protocols.

, , and . Future Gener. Comput. Syst., 13 (6): 469-487 (1998)

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Enhancing Last-Level Cache Performance by Block Bypassing and Early Miss Determination., and . Asia-Pacific Computer Systems Architecture Conference, volume 4186 of Lecture Notes in Computer Science, page 52-66. Springer, (2006)QoS-Driven Coordinated Management of Resources to Save Energy in Multi-core Systems., , and . IPDPS, page 303-313. IEEE, (2019)A compiler algorithm that reduces read latency in ownership-based cache coherence protocols., and . PACT, page 69-78. IFIP Working Group on Algol / ACM, (1995)Coordinated Management of DVFS and Cache Partitioning under QoS Constraints to Save Energy in Multi-Core Systems., , , and . CoRR, (2019)The Velox Transactional Memory Stack., , , , , , , , , and 14 other author(s). IEEE Micro, 30 (5): 76-87 (2010)Introduction to the special issue on high-performance and embedded architectures and compilers., and . ACM Trans. Archit. Code Optim., 8 (4): 18:1-18:2 (2012)Approx-RM: Reducing Energy on Heterogeneous Multicore Processors under Accuracy and Timing Constraints., , and . ACM Trans. Archit. Code Optim., 20 (3): 44:1-44:25 (September 2023)ZEBRA: Data-Centric Contention Management in Hardware Transactional Memory., , , , and . IEEE Trans. Parallel Distributed Syst., 25 (5): 1359-1369 (2014)Trends on heterogeneous and innovative hardware and software systems., , , , and . J. Parallel Distributed Comput., (2019)Introduction., , , , and . J. Parallel Distributed Comput., 66 (5): 615-616 (2006)