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Disambiguation of "Hayashi, Terumine"

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A Test Cost Reduction Method by Test Response and Test Vector Overlapping for Full-Scan Test Architecture.

, , , , and . Asian Test Symposium, page 366-371. IEEE Computer Society, (2005)

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Ken Hayashi

Mutsumi Hayashi

Akiko Hayashi

Tetsuhiro Hayashi

Yoshiki Hayashi

 

Other publications of authors with the same name

Descriptive Answer Clustering System for Immediate Feedback., , , , and . ICCE, volume 162 of Frontiers in Artificial Intelligence and Applications, page 37-40. IOS Press, (2007)A Method for Evaluating Upper Bound of Simultaneous Switching Gates Using Circuit Partition., , , and . ASP-DAC, page 291-294. IEEE Computer Society, (1999)An enhanced iterative improvement method for evaluating the maximum number of simultaneous switching gates for combinational circuits., , , and . ASP-DAC, page 107-112. IEEE, (1997)Evaluation Function for Fault Tolerant Multi-Layer Neural Networks., , , and . IJCNN (3), page 521-526. IEEE Computer Society, (2000)0-7695-0619-4.Test data compression technique using selective don't-care identification., , , , and . ASP-DAC, page 230-233. IEEE Computer Society, (2004)On a Logical Fault Model H1SGLF for Enhancing Defect Coverage., , , and . Asian Test Symposium, page 102-107. IEEE Computer Society, (1998)Between-Core Vector Overlapping for Test Cost Reduction in Core Testing., , , , and . Asian Test Symposium, page 268-273. IEEE Computer Society, (2003)Manipulation of hidden units activities for fault tolerant multi-layer neural networks., , , and . CIRA, page 19-24. IEEE, (2003)Enhancing both generalization and fault tolerance of multilayer neural networks., , , and . IJCNN, page 1429-1433. IEEE, (2007)LSI module placement methods using neural computation networks., , and . IJCNN, page 831-836. IEEE, (1990)