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15.5 A 930mW 69dB-DR 465MHz-BW CT 1-2 MASH ADC in 28nm CMOS., , , , , , , , , and . ISSCC, page 278-279. IEEE, (2016)Incremental Data Converters at Low Oversampling Ratios., and . IEEE Trans. Circuits Syst. I Regul. Pap., 57-I (7): 1525-1537 (2010)A -89-dBc IMD3 DAC Sub-System in a 465-MHz BW CT Delta-Sigma ADC Using a Power and Area Efficient Calibration Technique., , , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 65-II (7): 859-863 (2018)Adaptive digital noise-cancellation filtering using cross-correlators for continuous-time MASH ADC in 28nm CMOS., , , , , , , , , and . CICC, page 1-4. IEEE, (2017)A Reconfigurable ΔΣ ADC With Up to 100 MHz Bandwidth Using Flash Reference Shuffling., , and . IEEE Trans. Circuits Syst. I Regul. Pap., 61-I (8): 2263-2271 (2014)Some Extensions of the Crouzeix-Palencia Result., , and . SIAM J. Matrix Anal. Appl., 39 (2): 769-780 (2018)A time-interleaved continuous-time ΔΣ modulator with 20-MHz signal bandwidth., and . IEEE J. Solid State Circuits, 41 (7): 1578-1588 (2006)A 72 dB-DR 465 MHz-BW Continuous-Time 1-2 MASH ADC in 28 nm CMOS., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 51 (12): 2917-2927 (2016)An 8th-order MASH delta-sigma with an OSR of 3., and . ESSCIRC, page 476-479. IEEE, (2009)A DC-to-1 GHz Tunable RF Delta Sigma ADC Achieving DR = 74 dB and BW = 150 MHz at f0 = 450 MHz Using 550 mW., , , , , , , and . IEEE J. Solid State Circuits, 47 (12): 2888-2897 (2012)