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Disambiguation of "Kong, Jun Jin"

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A post-processing algorithm for reducing strong error effects in NAND flash memory.

, , , , , , , , , and . APCCAS, page 465-468. IEEE, (2016)

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Jin-Jun Liang

Eui-Jin Jun

Thay Kong

Xiangqing Kong

Seunghyun Kong

 

Other publications of authors with the same name

Error control coding and signal processing for flash memories., , , and . ISCAS, page 409-412. IEEE, (2012)High-speed add-compare-select units using locally self-resetting CMOS., , , and . ISCAS (1), page 889-892. IEEE, (2002)A 16-GB 640-GB/s HBM2E DRAM With a Data-Bus Window Extension Technique and a Synergetic On-Die ECC Scheme., , , , , , , , , and 16 other author(s). IEEE J. Solid State Circuits, 56 (1): 199-211 (2021)A post-processing algorithm for reducing strong error effects in NAND flash memory., , , , , , , , , and . APCCAS, page 465-468. IEEE, (2016)A modified two-step SOVA-based turbo decoder with a fixed scaling factor., , , and . ISCAS, page 37-40. IEEE, (2000)Low-latency architectures for high-throughput rate Viterbi decoders., and . IEEE Trans. Very Large Scale Integr. Syst., 12 (6): 642-651 (2004)Interleaved Convolutional Code and Its Viterbi Decoder Architecture., and . EURASIP J. Adv. Signal Process., 2003 (13): 1328-1334 (2003)CSI-aided Demapping of Dual-Carrier Modulation for Multiband-OFDM., , , and . ISCAS, page 2088-2091. IEEE, (2007)Efficient decoding of block turbo codes., , and . J. Commun. Networks, 20 (4): 345-353 (2018)22.1 A 1.1V 16GB 640GB/s HBM2E DRAM with a Data-Bus Window-Extension Technique and a Synergetic On-Die ECC Scheme., , , , , , , , , and 25 other author(s). ISSCC, page 330-332. IEEE, (2020)