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Disambiguation of "Emer, Joel S."

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Techniques to Reduce the Soft Error Rate of a High-Performance Microprocessor.

, , , and . ISCA, page 264-275. IEEE Computer Society, (2004)

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Wolfgang Emer

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Other publications of authors with the same name

Design analysis of a heterogeneous distributed system., and . ACM SIGOPS European Workshop, ACM, (1986)Unlocking Ordered Parallelism with the Swarm Architecture., , , , and . IEEE Micro, 36 (3): 105-117 (2016)An Architecture-Level Energy and Area Estimator for Processing-In-Memory Accelerator Designs., , and . ISPASS, page 116-118. IEEE, (2020)Symphony: Orchestrating Sparse and Dense Tensors with Hierarchical Heterogeneous Processing., , , , , , , , , and 2 other author(s). ACM Trans. Comput. Syst., (2023)Shared Resources for Multiple Instruction Stream Pipelined Processors. University of Illinois Urbana-Champaign, USA, (1979)Sparseloop: An Analytical, Energy-Focused Design Space Exploration Methodology for Sparse Tensor Accelerators., , , , and . ISPASS, page 232-234. IEEE, (2021)Accelerating RTL Simulation with Hardware-Software Co-Design., , , , , and . MICRO, page 153-166. ACM, (2023)HighLight: Efficient and Flexible DNN Acceleration with Hierarchical Structured Sparsity., , , , , and . MICRO, page 1106-1120. ACM, (2023)A scalable architecture for ordered parallelism., , , , and . MICRO, page 228-241. ACM, (2015)Accelerating Sparse Data Orchestration via Dynamic Reflexive Tiling (Extended Abstract)., , , , , , , , , and 1 other author(s). HOPC@SPAA, page 15-16. ACM, (2023)