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Disambiguation of "Lin, Chien-Ching"

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A low power turbo/Viterbi decoder for 3GPP2 applications.

, , , and . IEEE Trans. Very Large Scale Integr. Syst., 14 (4): 426-430 (2006)

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Chien-Tai Lin

Chia-Ching Lin

Ching-Chung Lin

Ching-Kuo Lin

Ching Yu Lin

 

Other publications of authors with the same name

Self-Compensation Technique for Simplified Belief-Propagation Algorithm., , , and . IEEE Trans. Signal Process., 55 (6-2): 3061-3072 (2007)Turbo Decoder Using Contention-Free Interleaver and Parallel Architecture., , , , and . IEEE J. Solid State Circuits, 45 (2): 422-432 (2010)A dual mode channel decoder for 3GPP2 mobile wireless communications., , , and . ESSCIRC, page 483-486. IEEE, (2004)A low power turbo/Viterbi decoder for 3GPP2 applications., , , and . IEEE Trans. Very Large Scale Integr. Syst., 14 (4): 426-430 (2006)A Universal VLSI Architecture for Reed-Solomon Error-and-Erasure Decoders., , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 56-I (9): 1960-1967 (2009)A low power and high speed Viterbi decoder chip for WLAN applications., , and . ESSCIRC, page 723-726. IEEE, (2003)Multi-mode message passing switch networks applied for QC-LDPC decoder., , , , and . ISCAS, page 752-755. IEEE, (2008)Multi-level memory systems using error control codes., , , , and . ISCAS (2), page 393-396. IEEE, (2004)A 1.8V 250mW COFDM baseband receiver for DVB-T/H applications., , , , , , , , , and . ISSCC, page 1002-1011. IEEE, (2006)A power and area efficient multi-mode FEC processor., , , and . ISCAS (2), page 253-256. IEEE, (2004)