( en | de | ru )

 

Disambiguation of "Cho, Lan-Chou"

Author of the publication

copydeleteadd this publication to your clipboard
A 50.8-53-GHz Clock Generator Using a Harmonic-Locked PD in 0.13- mum CMOS.

, , , and . IEEE Trans. Circuits Syst. II Express Briefs, 55-II (5): 404-408 (2008)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Abhik Narayan Choudhury

Yang-Yi Chou

Faris Choukér

Faris Choukér

Liang-Han Chou

 

Other publications of authors with the same name

An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with -55 dBc Fractional and -91 dBc Reference Spurs., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 65-I (11): 3756-3768 (2018)A 50.8-53-GHz Clock Generator Using a Harmonic-Locked PD in 0.13- mum CMOS., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 55-II (5): 404-408 (2008)A Fully Integrated Bluetooth Low-Energy Transmitter in 28 nm CMOS With 36% System Efficiency at 3 dBm., , , , , , , and . IEEE J. Solid State Circuits, 51 (7): 1547-1565 (2016)A 0.27mm2 13.5dBm 2.4GHz all-digital polar transmitter using 34%-efficiency Class-D DPA in 40nm CMOS., , , , , , , , , and 6 other author(s). ISSCC, page 342-343. IEEE, (2013)A Bluetooth Low-Energy Transceiver With 3.7-mW All-Digital Transmitter, 2.75-mW High-IF Discrete-Time Receiver, and TX/RX Switchable On-Chip Matching Network., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 52 (4): 1144-1162 (2017)A 33.6-to-33.8 Gb/s Burst-Mode CDR in 90 nm CMOS Technology., , , and . IEEE J. Solid State Circuits, 44 (3): 775-783 (2009)A 33.6-to-33.8Gb/s Burst-Mode CDR in 90nm CMOS., , and . ISSCC, page 48-586. IEEE, (2007)3.5mW W-Band Frequency Divider with Wide Locking Range in 90nm CMOS Technology., , , and . ISSCC, page 466-467. IEEE, (2008)A Bluetooth low-energy (BLE) transceiver with TX/RX switchable on-chip matching network, 2.75mW high-IF discrete-time receiver, and 3.6mW all-digital transmitter., , , , , , , , , and 1 other author(s). VLSI Circuits, page 1-2. IEEE, (2016)A 44GHz Dual-Modulus Divide-by-4/5 Prescaler in 90nm CMOS Technology., , and . CICC, page 397-400. IEEE, (2006)