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Design of Flexible Hardware Accelerators for Image Convolutions and Transposed Convolutions.

, , and . J. Imaging, 7 (10): 210 (2021)

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A High-Speed FPGA-Based True Random Number Generator Using Metastability With Clock Managers., , , and . IEEE Trans. Circuits Syst. II Express Briefs, 70 (2): 756-760 (February 2023)Parallel architecture of power-of-two multipliers for FPGAs., , , and . IET Circuits Devices Syst., 14 (3): 381-389 (2020)An Efficient Hardware-Oriented Single-Pass Approach for Connected Component Analysis., , and . Sensors, 19 (14): 3055 (2019)A High-Performance and Power-Efficient SIMD Convolution Engine for FPGAs., , , and . ICECS, page 1-4. IEEE, (2020)An FPGA-Based Hardware Accelerator for the k-Nearest Neighbor Algorithm Implementation in Wearable Embedded Systems., , , and . AII, page 44-56. (2022)Connected Component Analysis for Traffic Sign Recognition Embedded Processing Systems., , , and . ICECS, page 749-752. IEEE, (2018)Approximate Down-Sampling Strategy for Power-Constrained Intelligent Systems., , and . IEEE Access, (2022)Aggressive Approximation of the SoftMax Function for Power-Efficient Hardware Implementations., , and . IEEE Trans. Circuits Syst. II Express Briefs, 69 (3): 1652-1656 (2022)Unlocking Efficiency in BNNs: Global by Local Thresholding for Analog-Based HW Accelerators., , , , and . IEEE J. Emerg. Sel. Topics Circuits Syst., 13 (4): 940-955 (December 2023)ERMES: Efficient Racetrack Memory Emulation System based on FPGA., , , and . FPL, page 342-349. IEEE, (2022)