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Design methodology for fault tolerant ASICs., , , and . DDECS, page 8-11. IEEE, (2012)Reconfigurable Low Power Architecture for Fault Tolerant Pseudo-Random number Generation., , , , and . Journal of Circuits, Systems, and Computers, (2014)Circuit-Level Simulation of the Single Event Transients in an On-Chip Single Event Latchup Protection Switch., , , , and . J. Electron. Test., 31 (3): 275-289 (2015)Simulation-Based Analysis of the Single Event Transient Response of a Single Event Latchup Protection Switch., , , , and . DDECS, page 255-258. IEEE Computer Society, (2015)Fault-tolerant TMR and DMR circuits with latchup protection switches., , and . Microelectron. Reliab., 54 (8): 1613-1626 (2014)Middleware switch ASIC implementation., , and . ICECS, page 695-698. IEEE, (2011)Focused pooling for objective quality estimation., and . ICIP, page 221-225. IEEE, (2013)A multi-banked shared-l1 cache architecture for tightly coupled processor clusters., , and . ISSoC, page 1-5. IEEE, (2012)Focused pooling for image fusion evaluation., and . Inf. Fusion, (2015)Human-Robot Analogy - How Physiology Shapes Human and Robot Motion., , , and . ECAL, page 136-143. MIT Press, (2013)