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Interconnect sizing and spacing with consideration of couplingcapacitance.

, , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 20 (9): 1164-1169 (2001)

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Wire width planning for interconnect performance optimization., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (3): 319-329 (2002)Interconnect Estimation and Dlanning for Deep Submicron Designs., and . DAC, page 507-510. ACM Press, (1999)Computational geometry based placement migration., , , and . ICCAD, page 41-47. IEEE Computer Society, (2005)Improved crosstalk modeling for noise constrained interconnect optimization., , and . ASP-DAC, page 373-378. ACM, (2001)Multilevel global placement with congestion control., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 22 (4): 395-409 (2003)Global interconnect sizing and spacing with consideration of coupling capacitance., , , and . ICCAD, page 628-633. IEEE Computer Society / ACM, (1997)Physical hierarchy generation with routing congestion control., , and . ISPD, page 36-41. ACM, (2002)Diffusion-based placement migration., , , and . DAC, page 515-520. ACM, (2005)Sensitivity guided net weighting for placement driven synthesis., , and . ISPD, page 10-17. ACM, (2004)Interconnect design for deep submicron ICs., , , , and . ICCAD, page 478-485. IEEE Computer Society / ACM, (1997)