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Enhancing Cross-ISA DBT Through Automatically Learned Translation Rules.

, , , and . ASPLOS, page 84-97. ACM, (2018)

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Measuring Microarchitectural Details of Multi- and Many-Core Memory Systems through Microbenchmarking., , , , , , and . ACM Trans. Archit. Code Optim., 11 (4): 55:1-55:26 (2014)PREDATOR: A Cache Side-Channel Attack Detector Based on Precise Event Monitoring., , , and . SEED, page 25-36. IEEE, (2022)Compiler Optimization of Memory-Resident Value Communication Between Speculative Threads., , , and . CGO, page 39-52. IEEE Computer Society, (2004)Enabling improved power management in multicore processors through clustered DVFS., , and . DATE, page 293-298. IEEE, (2011)Energy efficient speculative threads: dynamic thread allocation in Same-ISA heterogeneous multicore systems., , , and . PACT, page 453-464. ACM, (2010)Improving the performance of program monitors with compiler support in multi-core environment., and . IPDPS, page 1-12. IEEE, (2010)Exploiting Speculative Thread-Level Parallelism in Data Compression Applications., , and . LCPC, volume 4382 of Lecture Notes in Computer Science, page 126-140. Springer, (2006)NoC frequency scaling with flexible-pipeline routers., , , and . ISLPED, page 403-408. IEEE/ACM, (2011)Accelerating Data Race Detection Utilizing On-Chip Data-Parallel Cores., , and . RV, volume 8174 of Lecture Notes in Computer Science, page 201-218. Springer, (2013)New Attacks and Defenses for Randomized Caches., , , and . CoRR, (2019)