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System-on-chip test scheduling with reconfigurable core wrappers., и . IEEE Trans. Very Large Scale Integr. Syst., 14 (3): 305-309 (2006)Diagnosing At-Speed Scan BIST Circuits Using a Low Speed and Low Memory Tester., , , и . IEEE Trans. Very Large Scale Integr. Syst., 15 (7): 790-800 (2007)A Memory Grouping Method for Reducing Memory BIST Logic of System-on-Chips., , и . IEICE Trans. Inf. Syst., 89-D (4): 1490-1497 (2006)Synthesis and Enumeration of Generalized Shift Registers for Strongly Secure SR-Equivalents., и . IEICE Trans. Inf. Syst., 100-D (9): 2232-2236 (2017)Effective Domain Partitioning for Multi-Clock Domain IP Core Wrapper Design under Power Constraints., , , и . IEICE Trans. Inf. Syst., 91-D (3): 807-814 (2008)Acceleration of Test Generation for Sequential Circuits Using Knowledge Obtained from Synthesis for Testability., , , и . IEICE Trans. Inf. Syst., 90-D (1): 296-305 (2007)Power-Constrained Test Synthesis and Scheduling Algorithms for Non-Scan BIST-able RTL Data Paths., , , , и . IEICE Trans. Inf. Syst., 88-D (8): 1940-1947 (2005)A Method of Path Mapping from RTL to Gate Level and Its Application to False Path Identification., , и . IEICE Trans. Inf. Syst., 93-D (7): 1857-1865 (2010)Differential Behavior Equivalent Classes of Shift Register Equivalents for Secure and Testable Scan Design., , и . IEICE Trans. Inf. Syst., 94-D (7): 1430-1439 (2011)Strongly Secure Scan Design Using Generalized Feed Forward Shift Registers., и . IEICE Trans. Inf. Syst., 98-D (10): 1852-1855 (2015)