Author of the publication

High-throughput VLSI implementations of iterative decoders and related code construction problems.

, , , and . GLOBECOM, page 361-365. IEEE, (2004)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

 

Other publications of authors with the same name

A Digital Low Dropout (LDO) Voltage Regulator Using Pseudoflash Transistors., and . IEEE Trans. Very Large Scale Integr. Syst., 31 (12): 1960-1969 (December 2023)Architecture and 3D device simulation of a PIN diode-based Gamma radiation detector., , and . ACM Great Lakes Symposium on VLSI, page 329-330. ACM, (2013)A High-Speed Fully-Programmable VLSI Decoder for Regular LDPC Codes., , , , , and . ICASSP (3), page 972-975. IEEE, (2006)Efficient cancer therapy using Boolean networks and Max-SAT-based ATPG., and . GENSiPS, page 87-90. IEEE, (2011)An efficient pulse flip-flop based launch-on-shift scan cell., and . ISCAS, page 4105-4108. IEEE, (2010)Sorting Binary Numbers in Hardware - A Novel Algorithm and its Implementation., , and . ISCAS, page 2225-2228. IEEE, (2009)Highly parallel decoding of space-time codes on graphics processing units., , , , and . Allerton, page 1262-1269. IEEE, (2009)Scaled Population Division for Approximate Computing., , and . ISLPED, page 1-6. IEEE, (2023)Fast, Ring-Based Design of 3-D Stacked DRAM., and . IEEE Trans. Very Large Scale Integr. Syst., 27 (8): 1731-1741 (2019)A Novel Hybrid Parallel-Prefix Adder Architecture With Efficient Timing-Area Characteristic., and . IEEE Trans. Very Large Scale Integr. Syst., 16 (3): 326-331 (2008)