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Half VDD Clock-Swing Flip-Flop with Reduced Contention for up to 60% Power Saving in Clock Distribution.

D. Levacq, M. Yazid, H. Kawaguchi, M. Takamiya, and T. Sakurai. ESSCIRC, page 190-193. IEEE, (2007)

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Efficient Multiple-Valued Signed-Digit Full Adder Based on NDR MOS Structures and its Application to an N-bit Current-Mode Constant-Time Adder.D. Bol, I. Hassoune, D. Levacq, D. Flandre, and J. Legat. J. Multiple Valued Log. Soft Comput., 13 (1-2): 61-78 (2007)A Wide Range Spatial Frequency Analysis of Intra-Die Variations with 4-mm 4000 × 1 Transistor Arrays in 90nm CMOS.D. Levacq, T. Minakawa, M. Takamiya, and T. Sakurai. CICC, page 257-260. IEEE, (2007)Low Leakage SOI CMOS Static Memory Cell With Ultra-Low Power Diode.D. Levacq, V. Dessard, and D. Flandre. IEEE J. Solid State Circuits, 42 (3): 689-702 (2007)Backgate Bias Accelerator for sub-100 ns Sleep-to-Active Modes Transition Time.D. Levacq, M. Takamiya, and T. Sakurai. IEEE J. Solid State Circuits, 43 (11): 2390-2395 (2008)1/5 power reduction by global optimization based on fine-grained body biasing.Y. Nakamura, D. Levacq, L. Xiao, T. Minakawa, T. Niiyama, M. Takamiya, and T. Sakurai. CICC, page 547-550. IEEE, (2008)Ultra-low power flip-flops for MTCMOS circuits.D. Levacq, V. Dessard, and D. Flandre. ISCAS (5), page 4681-4684. IEEE, (2005)Half VDD Clock-Swing Flip-Flop with Reduced Contention for up to 60% Power Saving in Clock Distribution.D. Levacq, M. Yazid, H. Kawaguchi, M. Takamiya, and T. Sakurai. ESSCIRC, page 190-193. IEEE, (2007)

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Disambiguation of "Levacq, David"

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Half VDD Clock-Swing Flip-Flop with Reduced Contention for up to 60% Power Saving in Clock Distribution.

Please choose a person to relate this publication to

Jürgen Davids

Volker David

Bodo David

Erich David

Ernst David

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Levacq, David"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Half VDD Clock-Swing Flip-Flop with Reduced Contention for up to 60% Power Saving in Clock Distribution.

Please choose a person to relate this publication to

Jürgen Davids

Volker David

Bodo David

Erich David

Ernst David

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
Harvard
MSOffice XML

Half VDD Clock-Swing Flip-Flop with Reduced Contention for up to 60% Power Saving in Clock Distribution.