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Adapting Tomasulo's algorithm for bytecode folding based Java processors., , and . SIGARCH Comput. Archit. News, 29 (5): 1-8 (2001)VLSI design of an FFT processor network., and . Integr., 8 (3): 301-320 (1989)A Multiple-Access Pipeline Architecture for Digital Signal Processing., and . IEEE Trans. Computers, 37 (3): 283-290 (1988)Design of Low-Delay Perfect-Reconstruction FIR Filter Banks for Tree-Structured Subband Coders., , and . ISCAS, page 969-972. IEEE, (1995)VLSI Array Processors Implementation of Block-State IIR Digital Filtentrs., , and . ISCAS, page 267-270. IEEE, (1994)Design of low-delay two-channel FIR filter banks using constrained optimization., , and . Signal Process., 48 (3): 183-192 (1996)Design of low-delay two-channel FIR filter banks using constrained optimization, , and . Signal Processing, 48 (3): 183--192 (February 1996)Design of Novel Serial-Parallel Inner-Product Processors., , , and . ISCAS, page 55-58. IEEE, (1994)Efficient decimator and interpolator Array Structures., , and . Journal of Circuits, Systems, and Computers, 5 (2): 215-238 (1995)A tool for two's complement, bit-level, fixed-point simulation of digital filters., and . ICECS, page 587-590. IEEE, (2000)