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A fast heuristic approach for parametric yield enhancement of analog designs., , , and . ACM Trans. Design Autom. Electr. Syst., 17 (3): 35:1-35:20 (2012)ILP-based inter-die routing for 3D ICs., , , and . ASP-DAC, page 330-335. IEEE, (2011)An observability measure to enhance statement coverage metric for proper evaluation of verification completeness., , and . ASP-DAC, page 323-326. ACM Press, (2005)Peak wake-up current estimation at gate-level with standard library information., , , and . VLSI-DAT, page 1-4. IEEE, (2012)Simultaneous optimization for low dropout regulator and its error amplifier with process variation., , , , and . VLSI-DAT, page 1-4. IEEE, (2014)A novel design space reduction method for efficient simulation-based optimization., , , and . ISCAS, page 381-384. IEEE, (2014)Dynamic IR drop estimation at gate level with standard library information., , , and . ISCAS, page 2606-2609. IEEE, (2010)A novel approach for high-level power modeling of sequential circuits using recurrent neural networks., , and . ISCAS (4), page 3591-3594. IEEE, (2005)Levelized High-Level Current Model of Logic Blocks for Dynamic Supply Noise Analysis., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 31 (6): 845-857 (2012)Wire Load Oriented Analog Routing with Matching Constraints., , and . ACM Trans. Design Autom. Electr. Syst., 25 (6): 55:1-55:26 (2020)