( en | de | ru )

 

Disambiguation of "Homayoun, Houman"

Author of the publication

copydeleteadd this publication to your clipboard
Adaptive Bandwidth Management for Performance-Temperature Trade-offs in Heterogeneous HMC+DDRx Memory.

, , , , and . ACM Great Lakes Symposium on VLSI, page 391-396. ACM, (2015)

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed. You can also use the button next to the name to display some publications already assigned to the person.

Houman Jalaie

Houman Alborzi

Houman Liaghati

Houman Tavassol

Homayoun Tadjadod

 

Other publications of authors with the same name

Advanced Reinforcement Learning Solution for Clock Skew Engineering: Modified Q-Table Update Technique for Peak Current and IR Drop Minimization., , , , , , , and . IEEE Access, (2023)Adversarial Attacks Against Machine Learning-Based Resource Provisioning Systems., , , , , , , and . IEEE Micro, 43 (5): 35-44 (September 2023)Breaking the Design and Security Trade-off of Look-up-table-based Obfuscation., , , , , , and . ACM Trans. Design Autom. Electr. Syst., 27 (6): 56:1-56:29 (2022)Large Language Models for Code Analysis: Do LLMs Really Do Their Job?, , , , , , , , , and 1 other author(s). CoRR, (2023)Fuzzing BusyBox: Leveraging LLM and Crash Reuse for Embedded Bug Unearthing., , , , , and . CoRR, (2024)ICNN: The Iterative Convolutional Neural Network., , and . ACM Trans. Embed. Comput. Syst., 18 (6): 119:1-119:27 (2020)A+ Tuning: Architecture+Application Auto-Tuning for In-Memory Data-Processing Frameworks., , and . ICPADS, page 163-166. IEEE, (2019)History & Variation Trained Cache (HVT-Cache): A process variation aware and fine grain voltage scalable cache with active access history monitoring., , , , and . ISQED, page 498-505. IEEE, (2012)A fault tolerant cache architecture for sub 500mV operation: resizable data composer cache (RDC-cache)., , , and . CASES, page 251-260. ACM, (2009)Post-synthesis sleep transistor insertion for leakage power optimization in clock tree networks., , , , and . ISQED, page 499-507. IEEE, (2010)