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EXPRESS-1: a dynamically reconfigurable platform using embedded processor FPGA., , , , , and . FPT, page 209-216. IEEE, (2004)Blokus Duo engine on a Zynq., , , , , and . FPT, page 374-377. IEEE, (2014)hCODE: An open-source platform for FPGA accelerators., , , , , and . FPT, page 205-208. IEEE, (2016)Power-aware FPGA routing fabrics and design tools., , , , , and . VLSI-SoC, page 67-72. IEEE, (2010)A Study of Heterogeneous Computing Design Method based on Virtualization Technology., , , , and . SIGARCH Comput. Archit. News, 44 (4): 86-91 (2016)A reconfigurable Java accelerator with software compatibility for embedded systems., , , , and . SIGARCH Comput. Archit. News, 41 (5): 71-76 (2013)Fault Recovery Technique for TMR Softcore Processor System Using Partial Reconfiguration., , , , , , and . ICA3PP (1), volume 7439 of Lecture Notes in Computer Science, page 392-404. Springer, (2012)A Bitstream Relocation Technique to Improve Flexibility of Partial Reconfiguration., , , , and . ICA3PP (1), volume 7439 of Lecture Notes in Computer Science, page 139-152. Springer, (2012)Physical Fault Detection and Recovery Methods for System-LSI Loaded FPGA-IP Core., , , , , and . IEICE Trans. Inf. Syst., 100-D (4): 633-644 (2017)An automatic FPGA design and implementation framework., , , , and . FPL, page 1-4. IEEE, (2013)