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Reduction of Number of Paths to be Tested in Delay Testing.

, , and . J. Electron. Test., 16 (5): 477-485 (2000)

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Embedded Test Decompressor to Reduce the Required Channels and Vector Memory of Tester for Complex Processor Circuit., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 15 (5): 531-540 (2007)Resilience-Aware Frequency Tuning for Neural-Network-Based Approximate Computing Chips., , , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (10): 2736-2748 (2017)Why current secure scan designs fail and how to fix them?, , , and . Integr., (2017)A New Multiple-Round Dimension-Order Routing for Networks-on-Chip., , , and . IEICE Trans. Inf. Syst., 94-D (4): 809-821 (2011)Editorial for the special issue on reliability and power efficiency for HPC., , , , and . CCF Trans. High Perform. Comput., 3 (1): 1-3 (2021)HyCA: A Hybrid Computing Architecture for Fault-Tolerant Deep Learning., , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (10): 3400-3413 (2022)Statistical Modeling of Soft Error Influence on Neural Networks., , , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (11): 4152-4163 (November 2023)GPGPU-Based ATPG System: Myth or Reality?, , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (1): 239-247 (2020)A Fast Precision Tuning Solution for Always-On DNN Accelerators., , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 41 (5): 1236-1248 (2022)Software-Based Self-Testing Using Bounded Model Checking for Out-of-Order Superscalar Processors., , , , , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 39 (3): 714-727 (2020)