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Post-compilation optimization for multiple gains with pattern matching., , , , and . ACM SIGPLAN Notices, 40 (12): 14-23 (2005)Reasoning about timing behavior of digital circuits using symbolic event propagation and temporal logic., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 25 (9): 1793-1814 (2006)Increasing Search Efficiency Using Multiple Heuristics., , , and . Inf. Process. Lett., 30 (1): 33-36 (1989)Bounded delay timing analysis and power estimation using SAT., , and . Microelectron. J., 41 (5): 317-324 (2010)Solving Constraint Optimization Problems from CLP-Style Specifications Using Heuristic Search Techniques., , , , and . IEEE Trans. Knowl. Data Eng., 14 (2): 353-368 (2002)A framework for systematic validation and debugging of pipeline simulators., , , and . ACM Trans. Design Autom. Electr. Syst., 10 (3): 462-491 (2005)Auxiliary state machines + context-triggered properties in verification., , and . ACM Trans. Design Autom. Electr. Syst., 13 (4): 62:1-62:31 (2008)Scenario-based timing verification of multiprocessor embedded applications., , and . ACM Trans. Design Autom. Electr. Syst., 14 (3): 37:1-37:58 (2009)Sticky-ERfair: a task-processor affinity aware proportional fair scheduler., , and . Real Time Syst., 47 (4): 356-377 (2011)Algorithms for Searching Explicit AND/OR Graphs and their Applications to Problem Reduction Search.. Artif. Intell., 65 (2): 329-345 (1994)