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Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage.

M. Natsui, A. Tamakoshi, H. Honjo, T. Watanabe, T. Nasuno, C. Zhang, T. Tanigawa, H. Inoue, M. Niwa, T. Yoshiduka, Y. Noguchi, M. Yasuhira, Y. Ma, H. Shen, S. Fukami, H. Sato, S. Ikeda, H. Ohno, T. Endoh, and T. Hanyu. VLSI Circuits, page 1-2. IEEE, (2020)

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Akira Hayashima

Akira Hori

Akira Satake

Akira Yasui

Akira Hayashima

Other publications of authors with the same name

A 47.14-µW 200-MHz MOS/MTJ-Hybrid Nonvolatile Microcontroller Unit Embedding STT-MRAM and FPGA for IoT Applications.M. Natsui, D. Suzuki, A. Tamakoshi, T. Watanabe, H. Honjo, H. Koike, T. Nasuno, Y. Ma, T. Tanigawa, Y. Noguchi and 6 other author(s). IEEE J. Solid State Circuits, 54 (11): 2991-3004 (2019)Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage.M. Natsui, A. Tamakoshi, H. Honjo, T. Watanabe, T. Nasuno, C. Zhang, T. Tanigawa, H. Inoue, M. Niwa, T. Yoshiduka and 10 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)Scalable Hardware Architecture for Invertible Logic with Sparse Hamiltonian Matrices.N. Onizawa, A. Tamakoshi, and T. Hanyu. SiPS, page 1-6. IEEE, (2021)A sudden power-outage resilient nonvolatile microprocessor for immediate system recovery.N. Onizawa, A. Mochizuki, A. Tamakoshi, and T. Hanyu. NANOARCH, page 39-44. IEEE Computer Society, (2015)Hardware Acceleration of Large-Scale CMOS Invertible Logic Based on Sparse Hamiltonian Matrices.N. Onizawa, A. Tamakoshi, and T. Hanyu. IEEE Open J. Circuits Syst., (2021)Design of an Energy-Efficient True Random Number Generator Based on Triple Read-Write Data-Stream Multiplexing of MTJ Devices.A. Tamakoshi, N. Onizawa, H. Yamagata, H. Fujita, and T. Hanyu. NEWCAS, page 283-286. IEEE, (2020)An FPGA-Accelerated Fully Nonvolatile Microcontroller Unit for Sensor-Node Applications in 40nm CMOS/MTJ-Hybrid Technology Achieving 47.14μW Operation at 200MHz.M. Natsui, D. Suzuki, A. Tamakoshi, T. Watanabe, H. Honjo, H. Koike, T. Nasuno, Y. Ma, T. Tanigawa, Y. Noguchi and 6 other author(s). ISSCC, page 202-204. IEEE, (2019)Dual-Port SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations Under Field-Assistance-Free Condition.M. Natsui, A. Tamakoshi, H. Honjo, T. Watanabe, T. Nasuno, C. Zhang, T. Tanigawa, H. Inoue, M. Niwa, T. Yoshiduka and 10 other author(s). IEEE J. Solid State Circuits, 56 (4): 1116-1128 (2021)Sudden Power-Outage Resilient In-Processor Checkpointing for Energy-Harvesting Nonvolatile Processors.N. Onizawa, A. Mochizuki, A. Tamakoshi, and T. Hanyu. IEEE Trans. Emerg. Top. Comput., 5 (2): 151-163 (2017)Stochastic behavior-considered VLSI CAD environment for MTJ/MOS-hybrid microprocessor design.M. Natsui, A. Tamakoshi, A. Mochizuki, H. Koike, H. Ohno, T. Endoh, and T. Hanyu. ISCAS, page 1878-1881. IEEE, (2016)

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Disambiguation of "Tamakoshi, Akira"

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Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage.

Please choose a person to relate this publication to

Akira Hayashima

Akira Hori

Akira Satake

Akira Yasui

Akira Hayashima

Other publications of authors with the same name

Disambiguation

BibSonomy

Disambiguation of "Tamakoshi, Akira"

copydeleteadd this publication to your clipboardcommunity posthistory of this postURLDOIBibTeXEndNoteAPAChicagoDIN 1505HarvardMSOffice XML Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage.

Please choose a person to relate this publication to

Akira Hayashima

Akira Hori

Akira Satake

Akira Yasui

Akira Hayashima

Other publications of authors with the same name

Disambiguation

copy delete add this publication to your clipboard
community post
history of this post
URL
DOI
BibTeX
EndNote
APA
Chicago
DIN 1505
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MSOffice XML

Dual-Port Field-Free SOT-MRAM Achieving 90-MHz Read and 60-MHz Write Operations under 55-nm CMOS Technology and 1.2-V Supply Voltage.