From post

Please choose a person to relate this publication to

To differ between persons with the same name, the academic degree and the title of an important publication will be displayed.

 

Другие публикации лиц с тем же именем

A Modified Signal Flow Graph and Corresponding Conflict-Free Strategy for Memory-Based FFT Processor Design., , , , , и . IEEE Trans. Circuits Syst. II Express Briefs, 66-II (1): 106-110 (2019)LEAPS: Topological-Layout-Adaptable Multi-die FPGA Placement for Super Long Line Minimization., , , , и . CoRR, (2023)Imbalanced Large Graph Learning Framework for FPGA Logic Elements Packing Prediction., , , , и . CoRR, (2023)Detailed Routing Short Violation Prediction Using Graph-Based Deep Learning Model., , , , , и . IEEE Trans. Circuits Syst. II Express Briefs, 69 (2): 564-568 (2022)LEAPS: Topological-Layout-Adaptable Multi-Die FPGA Placement for Super Long Line Minimization., , , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 71 (3): 1259-1272 (марта 2024)OpenPARF: An Open-Source Placement and Routing Framework for Large-Scale Heterogeneous FPGAs with Deep Learning Toolkit., , , , , и . ASICON, стр. 1-4. IEEE, (2023)A memory-based FFT processor using modified signal flow graph with novel conflict-free address schemes., , , , , и . IEICE Electron. Express, 14 (15): 20170660 (2017)Erratum: A memory-based FFT processor using modified signal flow graph with novel conflict-free address schemes IEICE Electronics Express Vol. 14 (2017) No. 15 pp. 20170660., , , , , и . IEICE Electron. Express, 14 (22): 20178005 (2017)A High Precision CV Control Scheme for Low Power AC-DC BUCK Converter Controller., , , , , , и . IEEE Trans. Circuits Syst. I Regul. Pap., 70 (10): 4183-4193 (октября 2023)LC-KO: A congestion-aware and area&timing-oriented placement method., , , , и . ASICON, стр. 1-4. IEEE, (2015)