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A configurable SIMD architecture with explicit datapath for intelligent learning., , , , , , , and . SAMOS, page 156-163. IEEE, (2016)A Middleware Approach to Achieving Fault Tolerance of Kahn Process Networks on Networks on Chips., , and . Int. J. Reconfigurable Comput., (2011)A compilation technique and performance profits for VLIW with heterogeneous vectors., and . MECO, page 9-12. IEEE, (2015)An Access-Pattern-Aware On-Chip Vector Memory System with Automatic Loading for SIMD Architectures., , , , and . HPEC, page 1-7. IEEE, (2018)Mixed-length SIMD code generation for VLIW architectures with multiple native vector-widths., , , , , and . ASAP, page 181-188. IEEE Computer Society, (2015)Rapid and accurate energy estimation of vector processing in VLIW ASIPs., , and . MECO, page 33-37. IEEE, (2013)A Task-aware Middleware for Fault-tolerance and Adaptivity of Kahn Process Networks on Network-on-Chip., and . ReCoSoC, volume 7551 of KIT Scientific Reports, page 73-78. KIT Scientific Publishing, (2010)Construction and exploitation of VLIW asips with multiple vector-widths., , , and . MECO, page 244-247. IEEE, (2014)BuildMaster: Efficient ASIP architecture exploration through compilation and simulation result caching., , , and . DDECS, page 83-88. IEEE Computer Society, (2014)