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Hardware Accelerator Framework Approach for Dynamic Partial Reconfigurable Overlays on Xilinx PYNQ., , and . GI-Jahrestagung, volume P-275 of LNI, page 481-492. GI, (2017)Redesign of an educational robot platform using web-based programming., , , , , and . WESE, page 3:1-3:8. ACM, (2016)A Hardware/Software Co-Design Approach for Control Applications with Static Real-Time Reallocation., , and . IPDPS Workshops, page 241-246. IEEE Computer Society, (2016)FGPU: An SIMT-Architecture for FPGAs., , and . FPGA, page 254-263. ACM, (2016)The value of FPGAs as reconfigurable hardware enabling Cyber-Physical Systems., , , and . ETFA, page 1-8. IEEE, (2015)An AXI compatible cypress EZ-USB FX3 interface for USB-3.0 SuperSpeed., , and . ReConFig, page 1-4. IEEE, (2014)A dynamic partial reconfigurable overlay concept for PYNQ., , and . FPL, page 1-4. IEEE, (2017)Floating-Point Arithmetic Using GPGPU on FPGAs., , and . ISVLSI, page 134-139. IEEE Computer Society, (2017)Hardware/Software virtualization in complex embedded systems.. Ruhr University Bochum, Germany, (2019)A Dynamic Partial Reconfigurable Overlay Framework for Python., , , and . ARC, volume 10824 of Lecture Notes in Computer Science, page 331-342. Springer, (2018)