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Sub-threshold Circuit Design with Shrinking CMOS Devices., , , and . ISCAS, page 2541-2544. IEEE, (2009)New category of ultra-thin notchless 6T SRAM cell layout topologies for sub-22nm., and . ISQED, page 425-430. IEEE, (2011)A half-micron CMOS logic generation., , , , , , , , , and 14 other author(s). IBM J. Res. Dev., 39 (1-2): 215-228 (1995)Nonrandom Device Mismatch Considerations in Nanoscale SRAM., , , and . IEEE Trans. Very Large Scale Integr. Syst., 20 (7): 1211-1220 (2012)An Extrinsic Device and Leakage Mechanism in Advanced Bulk FinFET SRAM., , , , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (8): 1819-1827 (2019)Bias-Induced Healing of $V_min$ Failures in Advanced SRAM Arrays., , , , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 25 (2): 660-669 (2017)Bias-Dependent Variation in FinFET SRAM., , , , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 28 (5): 1341-1344 (2020)Improving SRAM Vmin and yield by using variation-aware BTI stress., , , , , and . CICC, page 1-4. IEEE, (2010)Limits of bias based assist methods in nano-scale 6T SRAM., , , and . ISQED, page 1-8. IEEE, (2010)HTOL SRAM Vmin shift considerations in scaled HKMG technologies., , , , , , , , , and 2 other author(s). CICC, page 1-4. IEEE, (2014)