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Exploring Multi-Reader Buffers and Channel Placement During Dataflow Network Mapping to Heterogeneous Many-Core Systems., , and . IEEE Access, (2024)FPGA/GPU-based Acceleration for Frequent Itemsets Mining: A Comprehensive Review., , , , , and . ACM Comput. Surv., 54 (9): 179:1-179:35 (2022)Hardware Architectures for Frequent Itemset Mining Based on Equivalence Classes Partitioning., , and . IPDPS Workshops, page 289-294. IEEE Computer Society, (2016)Compilation of Dataflow Applications for Multi-Cores using Adaptive Multi-Objective Optimization., , , , , , and . ACM Trans. Design Autom. Electr. Syst., 24 (3): 29:1-29:23 (2019)Throughput and Memory Optimization for Parallel Implementations of Dataflow Networks Using Multi-Reader Buffers., , and . NG-RES@HiPEAC, volume 108 of OASIcs, page 6:1-6:13. Schloss Dagstuhl - Leibniz-Zentrum für Informatik, (2023)Model-Based Design Automation of Hardware/Software Co-Designs for Xilinx Zynq PSoCs., , , , , , and . ReConFig, page 1-8. IEEE, (2018)On the Analytic Evaluation of Schedules via Max-Plus Algebra for DSE of Multi-Core Architectures., , , and . SCOPES, page 63-71. ACM, (2019)On the design of hardware architectures for parallel frequent itemsets mining., , , , and . Expert Syst. Appl., (2020)A novel partition strategy for efficient implementation of 3D Cellular Genetic Algorithms., , , , and . Microprocess. Microsystems, (2024)Efficient Table-based Function Approximation on FPGAs using Interval Splitting and BRAM Instantiation., , and . CoRR, (2022)