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A Cross-layer Cognitive Radio Testbed for the Evaluation of Spectrum Sensing Receiver and Interference Analysis., , , , , , and . CrownCom, page 1-6. IEEE, (2008)Design Rule Evaluation Framework Using Automatic Cell Layout Generator for Design Technology Co-Optimization., , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 27 (8): 1933-1946 (2019)Switching pMOS Sense Amplifier for High-Density Low-Voltage Single-Ended SRAM., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (6): 1555-1563 (2015)Offset-Compensated Cross-Coupled PFET Bit-Line Conditioning and Selective Negative Bit-Line Write Assist for High-Density Low-Power SRAM., , , , , , and . IEEE Trans. Circuits Syst. I Regul. Pap., 62-I (4): 1062-1070 (2015)An Embedded Level-Shifting Dual-Rail SRAM for High-Speed and Low-Power Cache., , , , , and . IEEE Access, (2020)A Voltage and Temperature Tracking SRAM Assist Supporting 740mV Dual-Rail Offset for Low-Power and High-Performance Applications in 7nm EUV FinFET Technology., , , , , , , , , and 9 other author(s). ISSCC, page 392-394. IEEE, (2019)Pseudo NMOS based sense amplifier for high speed single-ended SRAM., , , , and . ICECS, page 331-334. IEEE, (2014)28-nm 1T-1MTJ 8Mb 64 I/O STT-MRAM with symmetric 3-section reference structure and cross-coupled sensing amplifier., , , , and . ISCAS, page 1-4. IEEE, (2017)A 0.65V embedded SDRAM with smart boosting and power management in a 45nm CMOS technology., , , , , , , , and . CICC, page 1-4. IEEE, (2012)Bitline Precharging and Preamplifying Switching pMOS for High-Speed Low-Power SRAM., , , , , , , and . IEEE Trans. Circuits Syst. II Express Briefs, 63-II (11): 1059-1063 (2016)