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Hardware Benchmarking of Round 2 Candidates in the NIST Lightweight Cryptography Standardization Process.

, , , , , , and . DATE, page 164-169. IEEE, (2021)

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A Multiplatform Parallel Approach for Lattice Sieving Algorithms., and . ICA3PP (1), volume 12452 of Lecture Notes in Computer Science, page 661-680. Springer, (2020)Reconfigurable hardware implementation of mesh routing in number field sieve factorization., , , and . FPT, page 263-270. IEEE, (2004)Exploiting system-level parallelism in the application development on a reconfigurable computer., , , , , and . FPT, page 443-446. IEEE, (2003)Option space exploration using distributed computing for efficient benchmarking of FPGA cryptographic modules., , , and . FPT, page 113-118. IEEE, (2012)Timing of Multi-Gigahertz Rapid Single Flux Quantum Digital Circuits., , and . VLSI Signal Processing, 16 (2-3): 247-276 (1997)A System-Level Design Methodology for Reconfigurable Computing Applications., , and . FPT, page 311-312. IEEE, (2005)Implementation of EAX Mode of Operation for FPGA Bitstream Encryption and Authentication., and . FPT, page 335-336. IEEE, (2005)Secure Partial Reconfiguration of FPGAs., and . FPT, page 155-162. IEEE, (2005)Comprehensive Evaluation of High-Speed and Medium-Speed Implementations of Five SHA-3 Finalists Using Xilinx and Altera FPGAs., , , , and . IACR Cryptology ePrint Archive, (2012)Very Compact FPGA Implementation of the AES Algorithm., and . CHES, volume 2779 of Lecture Notes in Computer Science, page 319-333. Springer, (2003)