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Disambiguation of "Sarwar, Syed Shakib"

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Gabor filter assisted energy efficient fast learning Convolutional Neural Networks.

, , and . ISLPED, page 1-6. IEEE, (2017)

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Syed Sarwar Lateef

Sarwar Syed Ali

Anas Sarwar

Asaf Sarwar

Ghulam Sarwar

 

Other publications of authors with the same name

DRESS: Dynamic REal-time Sparse Subnets., , , , , and . CoRR, (2022)Significance driven hybrid 8T-6T SRAM for energy-efficient synaptic storage in artificial neural networks., , , , and . DATE, page 151-156. IEEE, (2016)Enabling Spike-based Backpropagation in State-of-the-art Deep Neural Network Architectures., , and . CoRR, (2019)Exploring Memory-Oriented Design Optimization of Edge AI Hardware for Extended Reality Applications., , , , , and . IEEE Micro, 43 (6): 40-49 (November 2023)Energy-Efficient Neural Computing with Approximate Multipliers., , , , and . ACM J. Emerg. Technol. Comput. Syst., 14 (2): 16:1-16:23 (2018)Siracusa: A Low-Power On-Sensor RISC-V SoC for Extended Reality Visual Processing in 16nm CMOS., , , , , , , , , and 2 other author(s). ESSCIRC, page 217-220. IEEE, (2023)A Comprehensive Analysis on Adversarial Robustness of Spiking Neural Networks., , , , , and . IJCNN, page 1-8. IEEE, (2019)System-Level Design and Integration of a Prototype AR/VR Hardware Featuring a Custom Low-Power DNN Accelerator Chip in 7nm Technology for Codec Avatars., , , , , , , , , and 2 other author(s). CICC, page 1-8. IEEE, (2022)Multiplier-less Artificial Neurons exploiting error resiliency for energy-efficient neural computing., , , and . DATE, page 145-150. IEEE, (2016)Siracusa: A 16 nm Heterogenous RISC-V SoC for Extended Reality With At-MRAM Neural Engine., , , , , , , , , and 2 other author(s). IEEE J. Solid State Circuits, 59 (7): 2055-2069 (July 2024)