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Disambiguation of "Schreiter, Jörg"

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An MPSoC for energy-efficient database query processing.

, , , , , , , , , , , , , , , , , , , , , , , , and . DAC, page 112:1-112:6. ACM, (2016)

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Jörg Schreiter

Jörg Schreiter

Werner Jörg

Johannes-Richard Jörg

Edgar Jörg

 

Other publications of authors with the same name

How to Achieve World-Leading Energy Efficiency using 22FDX with Adaptive Body Biasing on an Arm Cortex-M4 IoT SoC., , , , , , , , , and 6 other author(s). ESSDERC, page 66-69. IEEE, (2019)An Analog VLSI Pulsed Neural Network for Image Segmentation Using Adaptive Connection Weights., , , , and . ICANN, volume 2415 of Lecture Notes in Computer Science, page 1293-1298. Springer, (2002)An Analog VLSI Pulsed Neural Network Implementation for Image Segmentation., , , and . PARELEC, page 51-55. IEEE Computer Society, (2004)High resolution ADPLL frequency synthesizer for FPGA-and ASIC-based applications., , , and . FPT, page 28-34. IEEE, (2003)Pulse coupled neural networks with adaptive synapses for image segmentation., , , , and . ARCS Workshops, volume P-41 of LNI, page 275-282. GI, (2004)Analog implementation for networks of integrate-and-fire neurons with adaptive local connectivity., , , , and . NNSP, page 657-666. IEEE, (2002)Cellular pulse-coupled neural network with adaptive weights for image segmentation and its VLSI implementation., , , , and . Image Processing: Algorithms and Systems, volume 5298 of SPIE Proceedings, page 290-296. SPIE, (2004)A 0.55V 6.3uW/MHz Arm Cortex-M4 MCU with Adaptive Reverse Body Bias and Single Rail SRAM., , , , , , , , , and . COOL CHIPS, page 1-3. IEEE, (2020)