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A Constraint Driven Approach to Loop Pipelining and Register Binding.

, , , , and . DATE, page 377-383. IEEE Computer Society, (1998)

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Iterative Probabilistic Performance Prediction for Multi-Application Multiprocessor Systems., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 29 (4): 538-551 (2010)Performance evaluation of concurrently executing parallel applications on multi-processor systems., , , and . ICSAMOS, page 100-107. IEEE, (2009)GPU-Vote: A Framework for Accelerating Voting Algorithms on GPU., , , and . Euro-Par, volume 7484 of Lecture Notes in Computer Science, page 945-956. Springer, (2012)Predictable Embedded Multiprocessor System Design., , , , , and . SCOPES, volume 3199 of Lecture Notes in Computer Science, page 77-91. Springer, (2004)Multi-processor System-level Synthesis for Multiple Applications on Platform FPGA., , , , and . FPL, page 92-97. IEEE, (2007)CA-MPSoC: An automated design flow for predictable multi-processor architectures for multiple applications., , , , and . J. Syst. Archit., 56 (7): 265-277 (2010)Constraint Analysis for DSP Code Generation., , , , and . ISSS, page 33-40. ACM / IEEE Computer Society, (1997)Run-time reconfiguration of communication in SIMD architectures., , , , and . IPDPS, IEEE, (2006)MOVE-Pro: A low power and high code density TTA architecture., , , and . ICSAMOS, page 294-301. IEEE, (2011)Reconfigurable Instruction-Set Application-Tuning for DSP., , , and . Journal of Circuits, Systems, and Computers, 12 (3): 333-352 (2003)