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Context-Aware Resiliency: Unequal Message Protection for Random-Access Memories.

, , , , , and . IEEE Trans. Inf. Theory, 65 (10): 6146-6159 (2019)

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Parity++: Lightweight Error Correction for Last Level Caches., , , and . DSN Workshops, page 114-120. IEEE Computer Society, (2018)Context-Aware Resiliency: Unequal Message Protection for Random-Access Memories., , , , , and . IEEE Trans. Inf. Theory, 65 (10): 6146-6159 (2019)Low-Cost Memory Fault Tolerance for IoT Devices., , , , and . ACM Trans. Embed. Comput. Syst., 16 (5s): 128:1-128:25 (2017)COMET: On-die and In-controller Collaborative Memory ECC Technique for Safer and Stronger Correction of DRAM Errors., and . DSN, page 124-136. IEEE, (2022)Lightweight Fault Tolerance in SRAM Based On-Chip Memories.. University of California, Los Angeles, USA, (2018)base-search.net (ftcdlib:qt1d95908z).Achieving DRAM-Like PCM by Trading Off Capacity for Latency., and . IEEE Trans. Computers, 73 (4): 1180-1189 (April 2024)DRDebug: Automated Design Rule Debugging., , , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 42 (2): 606-615 (February 2023)Designing a 2048-Chiplet, 14336-Core Waferscale Processor., , , , , , , , , and . DAC, page 1183-1188. IEEE, (2021)Error Correction and Detection for Computing Memories Using System Side Information., , , , and . ITW, page 1-5. IEEE, (2018)SAME-Infer: Software Assisted Memory Resilience for Efficient Inference at the Edge., and . MEMSYS, page 10-22. ACM, (2020)