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Improving tag generation for memory data authentication in embedded processor systems., , , and . ASP-DAC, page 50-55. IEEE, (2016)Unrolling Loops With Indeterminate Loop Counts in System Level Pipelines., and . ASP-DAC, page 99-104. IEEE, (1998)Switchable cache: utilising dark silicon for application specific cache optimisations., , , and . IET Comput. Digit. Tech., 10 (4): 157-164 (2016)HMP-ASIPs: heterogeneous multi-pipeline application-specific instruction-set processors., , , and . IET Comput. Digit. Tech., 3 (1): 94-108 (2009)Pairwise alignment of nucleotide sequences using maximal exact matches., , , and . BMC Bioinform., 20 (1): 261:1-261:15 (2019)LOP: A packet classification architecture with higher throughput and lower power consumption than TCAM., , and . Des. Autom. Embed. Syst., 14 (3): 231-263 (2010)Profiling in the ASP codesign environment., , and . J. Syst. Archit., 46 (14): 1263-1274 (2000)Custom Floating-Point Unit Generation for Embedded Systems., and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 28 (5): 638-650 (2009)iCETD: An improved tag generation design for memory data authentication in embedded processor systems., , , and . Integr., (2017)1LUTSensor: Detecting FPGA Voltage Fluctuations using LookUp Tables., , and . IACR Trans. Cryptogr. Hardw. Embed. Syst., 2024 (1): 51-86 (2024)