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Using Simulated Fault Injection for Fault Tolerance Assessment of Quantum Circuits.

, , , , and . Annual Simulation Symposium, page 213-220. IEEE Computer Society, (2007)

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Saboteur-Based Fault Injection for Quantum Circuits Fault Tolerance Assessment., , , , and . DSD, page 634-640. IEEE Computer Society, (2007)An FPGA sliding window-based architecture harris corner detector., , and . FPL, page 1-4. IEEE, (2014)Quantum circuit's reliability assessment with VHDL-based simulated fault injection., , , and . Microelectron. Reliab., 50 (2): 304-311 (2010)Layered LDPC decoder in-order message access scheduling: a case study., and . SACI, page 193-198. IEEE, (2020)Performance Enhancement of Serial Based FPGA Probabilistic Fault Emulation Techniques., , and . DDECS, page 149-152. IEEE Computer Society, (2015)Memory-Centric Flooded LDPC Decoder Architecture Using Non-surjective Finite Alphabet Iterative Decoding., , and . DSD, page 104-109. IEEE Computer Society, (2018)Direct FPGA-based power profiling for a RISC processor., , , , , , , , and . I2MTC, page 1578-1583. IEEE, (2015)Automatic Generation of FPGA Hardware Accelerators for Graphics Applications., and . PECCS, page 383-386. SciTePress, (2012)Generation of floating point 2D translation operators for FPGA., , and . SACI, page 289-294. IEEE, (2015)Template-based QC-LDPC decoder architecture generation., , and . ICICS, page 1-5. IEEE, (2015)