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A Novel Method to Improve the Test Efficiency of VLSI Tests.

, , and . ASP-DAC/VLSI Design, page 499-504. IEEE Computer Society, (2002)

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Table headers: An entrance to the data mine., and . ICPR, page 4065-4070. IEEE, (2016)Accurate computation of field reject ratio based on fault latency., , and . IEEE Trans. Very Large Scale Integr. Syst., 1 (4): 537-545 (1993)A system for recognizing a large class of engineering drawings., , and . IEEE Trans. Pattern Anal. Mach. Intell., 19 (8): 868-890 (1997)Programming pipelined CAD applications on message-passing architectures., , , , , and . Concurr. Pract. Exp., 7 (4): 315-337 (1995)A synthesis for testability scheme for finite state machines using clock control., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 18 (12): 1780-1792 (1999)Diagnosis of Faults in Linear Tree Networks., and . IEEE Trans. Computers, 26 (1): 29-33 (1977)A nonparametric classifier for unsegmented text., , , , , , and . DRR, volume 5296 of SPIE Proceedings, page 102-108. SPIE, (2004)Predicting Fault Coverage from Probabilistic Testability.. ITC, page 803-807. IEEE Computer Society, (1985)Clock partitioning for testability., , and . Great Lakes Symposium on VLSI, page 42-46. IEEE, (1993)High-level microprogramming: an optimizing C compiler for a processing element of a CAD accelerator., , and . MICRO, page 97-106. ACM/IEEE, (1990)