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Disambiguation of "Knag, Phil"

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Efficient Hardware Architecture for Sparse Coding.

, , , and . IEEE Trans. Signal Process., 62 (16): 4173-4186 (2014)

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Petter Knagenhjelm

Bernhard Knagge

Phil Zundel

Phil Langer

Phil Liebing

 

Other publications of authors with the same name

A 6.67mW sparse coding ASIC enabling on-chip learning and inference., , , and . VLSIC, page 1-2. IEEE, (2014)A 1.40mm2 141mW 898GOPS sparse neuromorphic processor in 40nm CMOS., , and . VLSI Circuits, page 1-2. IEEE, (2016)Memristive devices for stochastic computing., , , and . ISCAS, page 2592-2595. IEEE, (2014)A Sparse Coding Neural Network ASIC With On-Chip Learning for Feature Extraction and Encoding., , , and . IEEE J. Solid State Circuits, 50 (4): 1070-1079 (2015)A 1.5-GHz 6.144T Correlations/s 64 × 64 Cross-Correlator With 128 Integrated ADCs for Real-Time Synthetic Aperture Imaging., , , , , , , , , and 6 other author(s). IEEE J. Solid State Circuits, 52 (5): 1450-1457 (2017)Efficient Hardware Architecture for Sparse Coding., , , and . IEEE Trans. Signal Process., 62 (16): 4173-4186 (2014)A 640M pixel/s 3.65mW sparse event-driven neuromorphic object recognition processor with on-chip learning., , , and . VLSIC, page 50-. IEEE, (2015)A 617-TOPS/W All-Digital Binary Neural Network Accelerator in 10-nm FinFET CMOS., , , , , , , , , and 1 other author(s). IEEE J. Solid State Circuits, 56 (4): 1082-1092 (2021)An 8-core RISC-V Processor with Compute near Last Level Cache in Intel 4 CMOS., , , and . VLSI Technology and Circuits, page 68-69. IEEE, (2022)Low-Clock-Power Digital Standard Cell IPs for High-Performance Graphics/AI Processors in 10nm CMOS., , , , , , , , , and 6 other author(s). VLSI Circuits, page 1-2. IEEE, (2020)