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Test Scheduling of BISTed Memory Cores for SOC.

, , , , , , and . Asian Test Symposium, page 356-. IEEE Computer Society, (2002)

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Security Design for Configuration Management of Android Devices., and . COMPSAC Workshops, page 249-254. IEEE Computer Society, (2015)Fault Pattern Oriented Defect Diagnosis for Memories., , , , , , , and . ITC, page 29-38. IEEE Computer Society, (2003)An SOC Test Integration Platform and Its Industrial Realization., , , , , , , and . ITC, page 1213-1222. IEEE Computer Society, (2004)Test and Diagnosis of Word-Oriented Multiport Memories., , , and . VTS, page 248-253. IEEE Computer Society, (2003)Efficient Neighborhood Pattern-Sensitive Fault Test Algorithms for Semiconductor Memories., , and . VTS, page 225-230. IEEE Computer Society, (2001)FAME: A Fault-Pattern Based Memory Failure Analysis Framework., , , , , and . ICCAD, page 595-598. IEEE Computer Society / ACM, (2003)STEAC: A Platform for Automatic SOC Test Integration., , , , , , and . IEEE Trans. Very Large Scale Integr. Syst., 15 (5): 541-545 (2007)Neighborhood pattern-sensitive fault testing and diagnostics for random-access memories., , and . IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 21 (11): 1328-1336 (2002)Automatic Generation of Memory Built-in Self-Test Cores for System-on-Chip., , , , , and . Asian Test Symposium, page 91-96. IEEE Computer Society, (2001)Design and test of a scalable security processor., , , , and . ASP-DAC, page 372-375. ACM Press, (2005)